Synthesis of Mixed-CMOS Very Large-Signal Interconnects with Low Power Consumption

garima jain; amrita khera; akash gupta; sanjay sharma

doi:10.36948/ijfmr.2025.v07i04.52167

Synthesis of Mixed-CMOS Very Large-Signal Interconnects with Low Power Consumption

Author(s)	Ms. garima jain, Dr. amrita khera, Dr. akash gupta, Mr. sanjay sharma
Country	India
Abstract	1.Abstract-The use of portable devices and applications with a high data transfer rate has been on the rise recently. When it comes to low power applications, VLSI designers frequently choose for the static CMOS logic style. This form of logic does not suffer from signal noise integrity difficulties and dissipates very little power. But high performance circuits can't use designs built on this logic approach because they're so sluggish. Domino logic-style architectures, on the other hand, are space-efficient and produce excellent results. However, in comparison to static CMOS, they dissipate more power. When designing circuits, designers often combine different logic styles in a strategic way to reap the benefits of each. By combining the best features of static and Domino logic models in a well-designed mixed static Domino CMOS circuit, we may circumvent the limitations of each. We offer a technique for realizing a mixed static Domino circuit that relies on unate decomposition. Our approach breaks down Boolean circuits into their constituent unate and binate subblocks. The decomposition procedure finds the maximal unate set, which includes states that can materialize a Domino block, using an Influence table approach. In a further step, we try to determine which elements of the unate set are best realized by Domino logic and which ones should be realized by static logic. The next step is to map the Domino block that was obtained using a new on-the-fly mapping approach. We combine the nodes according to their functional qualities and pursue a node-by-node incremental mapping strategy. This continues until all of the cells have been filled up to their maximum allowed width and height. Next, we aim to minimize the area penalty and obtain an advantage in terms of time by selecting re-ordering the cells. To determine the best set of cells to reorder, we employ a two-objective optimization strategy.
Keywords	vlsi,circuits
Field	Engineering
Published In	Volume 7, Issue 4, July-August 2025
Published On	2025-07-25
DOI	https://doi.org/10.36948/ijfmr.2025.v07i04.52167
Short DOI	https://doi.org/g9vps7

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Synthesis of Mixed-CMOS Very Large-Signal Interconnects with Low Power Consumption

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