Pipelined AES-128 Encryption and Decryption Design Using Verilog HDL

Author(s)	Mr. Gokul R, Dr. Swarnalatha A
Country	India
Abstract	This paper presents a high-performance, fully pipelined AES-128 hardware implementation using Verilog HDL, designed for secure, high-throughput cryptographic applications. The architecture targets the Artix-7 Field Programmable Gate Array (FPGA) and features independent encryption and decryption datapaths, precomputed round keys stored in Block RAM (BRAM), and a 10-stage pipeline. The design achieves a throughput of 12.8 Gbps at 100 MHz with a 12-cycle latency. Modular Verilog blocks for SubBytes, ShiftRows, MixColumns, and AddRoundKey are optimized for scalability and resource efficiency. The implementation is verified through Register-Transfer Level (RTL) and gate-level simulations, ensuring compliance with the NIST FIPS-197 standard using standard, random, and edge-case test vectors. Synthesis results indicate 24.83% utilization of lookup tables (LUTs), 40% BRAM usage, 13.21% flip-flop utilization, and 1.12 W total power consumption. These results position the design as an efficient and scalable solution for secure Internet of Things (IoT) devices, VLSI systems, and high-speed communication platforms.
Keywords	AES-128, Verilog HDL, Pipelined Architecture, FPGA Implementation, Encryption, Decryption, Hardware Security, RTL Simulation
Field	Engineering
Published In	Volume 7, Issue 4, July-August 2025
Published On	2025-08-10
DOI	https://doi.org/10.36948/ijfmr.2025.v07i04.52209
Short DOI	https://doi.org/g9w5ft

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