Design of AI-Based Low Power VLSI Architecture for Smart Edge Devices

Author(s)	Dr. Priyanka Jaiswal, Dr. Sachin Bandewar
Country	India
Abstract	AI is everywhere, and IoT keeps getting bigger—so honestly, edge devices have to step up their game. In this paper, I’m laying out a low-power VLSI setup built for AI on these devices. The core is a lean neural processing unit (NPU) paired with optimized CMOS logic. Everything’s centered around slashing power use, reducing lag, and keeping computing strong. To get there, I used hybrid logic, added in approximate computing, and threw in power-saving moves like clock gating. When I ran the simulations, this architecture topped old-school VLSI designs in both energy savings and speed. So, it’s right for smart ag drones, wearables, and real-time monitoring systems.
Keywords	VLSI, Artificial Intelligence, Low Power Design, Edge Computing, Neural Processing Unit, CMOS
Field	Engineering
Published In	Volume 6, Issue 4, July-August 2024
Published On	2024-08-20

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