Polynomial Computation Using Multiplexer-Based Stochastic Logic in VLSI

Author(s)	Mr. konda pavan kumar, Mr. Garikapati Rajeev, Mr. Kapuluru Mohith Reddy, Prof. M Valarmathi
Country	India
Abstract	This paper presents a multiplexer-based stochastic computing architecture for efficient polynomial evaluation in VLSI systems. Conventional binary implementations of polynomial functions require complex hardware, leading to higher power consumption, area, and delay. To address this, the proposed method uses stochastic logic, where numbers are represented as probabilistic bit streams, enabling arithmetic operations using simple logic gates such as AND gates and multiplexers. Polynomial approximations of functions like e^x,e^−x, sinh(x), and cosh(x) are implemented using Taylor series and optimized through Horner’s rule. Simulation results demonstrate significant reductions in power, area, and delay compared to conventional methods, proving the effectiveness of stochastic computing for low-power, high-speed VLSI applications.
Keywords	Polynomial approximation, Horner's rule, Taylor series, VLSI architecture, exponential and hyperbolic functions, FPGA implementation, stochastic computing, multiplexer-based design, and low-power digital design.
Field	Engineering
Published In	Volume 8, Issue 3, May-June 2026
Published On	2026-05-05
DOI	https://doi.org/10.36948/ijfmr.2026.v08i03.75123

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