International Journal For Multidisciplinary Research

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Design and Implementation of UART protocol using Verilog

Author(s) Mr. Vinayak Sinha, Ms. Puja Priya, Mr. Nikhil Singh Negi, Ms. Tanuja Kumari, Ms. Shreyanshi Jaiswal
Country India
Abstract The given paper introduces a novel approach which involves the design and implementation of a UART (Universal Asynchronous Receiver/Transmitter) module with FIFO (First-In-First-Out) buffering, developed using Verilog HDL and verified on a Basys 3 FPGA board through Xilinx Vivado 2023.2.) UART is a standard serial communication interface used in embedded systems for reliable data exchange.
Keywords UART · Verilog HDL · FIFO · Oversampling · Baud rate generator · FPGA · Serial communication
Field Computer > Electronics
Published In Volume 8, Issue 3, May-June 2026
Published On 2026-05-03
DOI https://doi.org/10.36948/ijfmr.2026.v08i03.77157
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