
International Journal For Multidisciplinary Research
E-ISSN: 2582-2160
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Impact Factor: 9.24
A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal
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Volume 7 Issue 4
July-August 2025
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Design and Implementation of Memory Controller for Byte Access from Data Memory for SoC’s Devices
Author(s) | Ms. Preethi K, Ms. Pruthvika R, Vaishnavika S G, Vathsala H K, Prof. Manasa M G |
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Country | India |
Abstract | A System-on Modern computing systems, particularly System-on-Chip (SoC) architectures, incorporate multiple processors, integrated memory, and control logic to enhance efficiency. These architectures are prevalent in contemporary electronic devices like smartphones, tablets, and smartwatches, all of which demand high-performance memory management. Ensuring smooth data exchange within these memory-intensive devices is crucial for optimal functionality. This paper presents a specialized memory controller designed to regulate data transfer between multiple processors and peripheral components. The controller is based on the Advanced eXtensible Interface (AXI) protocol, which facilitates parallel communication between various SoC components. The proposed memory access controller (MAC) efficiently manages data transmission speeds, minimizes processor workload, and enhances overall system performance. |
Keywords | System-on-Chip (SoC), Advanced eXtensible Interface (AXI), Memory Access Controller (MAC) |
Field | Engineering |
Published In | Volume 7, Issue 3, May-June 2025 |
Published On | 2025-05-11 |
DOI | https://doi.org/10.36948/ijfmr.2025.v07i03.44553 |
Short DOI | https://doi.org/g9kfqz |
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E-ISSN 2582-2160

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IJFMR DOI prefix is
10.36948/ijfmr
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