Design and Implementation of SRAM using FinFET

Author(s)	Ms. Aaditri Singh, Mr. Kavyansh Saxena, Prof. Kanika Jindal
Country	India
Abstract	Abstract—With the continuous scaling of CMOS technology, traditional SRAM designs face challenges such as increased leakage current, reduced reliability, and higher power consumption. FinFET (Fin Field-Effect Transistor) technology has emerged as a promising alternative due to its superior electrostatic control, reduced leakage, and enhanced performance. This paper explores the implementation of SRAM using FinFET technology, analyzing its advantages over conventional bulk CMOS-based SRAM. We investigate key design considerations, including read/write stability, power efficiency, and performance metrics in different FinFET-based SRAM topologies. Simulation results demonstrate that FinFET SRAM exhibits lower leakage power, improved noise margins, and better scalability compared to traditional SRAM designs. Additionally, the impact of various process variations on FinFET SRAM performance is analyzed to assess its robustness in nanoscale circuits. The findings highlight FinFET’s potential to drive the next generation of low-power and high-performance memory architectures.
Keywords	Keywords— SRAM, FinFET, low-power memory, leakage reduction, nanoscale circuits, performance analysis
Field	Engineering
Published In	Volume 7, Issue 3, May-June 2025
Published On	2025-05-18
DOI	https://doi.org/10.36948/ijfmr.2025.v07i03.45128
Short DOI	https://doi.org/g9kt9v

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International Journal For Multidisciplinary Research