Techniques for Low-Power VLSI Systems: An Updated Overview

Author(s)	Badhon Saha, Mrinmoy Sarkar, Dr. Amana Yadav
Country	India
Abstract	There is a rising demand for energy-efficient electronic devices in the context of portable, high-performance, and strongly embedded systems that warrant a serious concern and emphasis on low power Very Large-Scale Integration design. With the scaling of semiconductor technology at an aggressive pace of advancement, raised integration density and higher operating speeds introduce serious difficulties and challenges in effective power consumption management. This review paper examines the basic concepts of low power VLSI design and discusses the causes of dynamic and static power dissipation. It provides a systematic examination of numerous methods of power optimization developed at different levels of abstraction, starting from process technologies to digital circuits and architectural and systems levels. It is an attempt to present an overall detailed insight and perspective of present methodologies and means available to design VLSI circuits able to deliver superior performance at substantially lower energy dissipation levels.
Keywords	CMOS Technology Advancements, Architectural Level, Power Gating, Pipelining and Parallel Processing, Multi-Threshold CMOS.
Field	Engineering
Published In	Volume 8, Issue 1, January-February 2026
Published On	2026-01-23
DOI	https://doi.org/10.36948/ijfmr.2026.v08i01.67155

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