Review of Low-Power CMOS Full Adder Using Hybrid Logic circuit

Author(s)	Dr. Priyanka Jaiswal, Dr. Sachin Bandewar
Country	India
Abstract	Low-power digital circuits play a crucial role in modern VLSI systems, particularly in portable and battery-powered devices. The full adder is a key arithmetic component widely used in arithmetic logic units (ALUs), multipliers, and digital signal processing systems. However, conventional CMOS full adder designs typically involve high power consumption and a large number of transistors. This paper proposes a low-power CMOS full adder based on hybrid logic techniques. The design integrates multiple logic styles, including complementary CMOS, pass transistor logic, and transmission gate logic, to minimize power usage, reduce propagation delay, and enhance overall performance. Simulation results indicate that the proposed design achieves improved power efficiency and faster operation compared to conventional full adders, making it well-suited for high-performance VLSI applications
Field	Engineering
Published In	Volume 6, Issue 5, September-October 2024
Published On	2024-10-11

About IJFMR Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics Peer Review & Plagiarism	Join as a Reviewer Editors & Reviewers Reviewer Referral Program Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us		+91-9687-828-838	editor@ijfmr.com

International Journal For Multidisciplinary Research