International Journal For Multidisciplinary Research

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Design and Implementation of AI Core Booting and Utilization in Versal AI FPGA VCK1902

Author(s) Mr. D G Harshith, Ms. Bhavya K B
Country India
Abstract As modern defense and edge computing applications rapidly scale complexity, Field Programmable Gate Array (FPGA) is evolving into heterogeneous Adaptive Compute Acceleration Platform (ACAP). The AMD Xilinx VCK1902 Versal integrates traditional scalar processing, adaptable programmable logic, and advanced vector processing Engine AI array. This paper details comprehensive design methodology to minimize computational bottlenecks and accelerate system initialization by heavily utilizing the capabilities of AI Core in the VCK1902 FPGA. By extracting a 33-tap, 512-window Symmetric FIR filter from traditional logic and deploying it directly as C++ graph on the Engine AI,successfully offloaded significant dig-ital signal processing overhead. Verified through the Vivado and Vitis 2022.2, the design met stringent timing limits with a Worst Negative Slack (WNS) of 6.214 ns at 100 MHz and requires only a fraction of the available Programmable Logic (0.25% LUT utilization). Mostly, the architectural optimizations accelerated the initialization phase; while the total Platform Loader and Manager (PLM) boot time was 782.549 ms, the customized project sequence has an AIE image load time of just 9.791 ms and a ROM ready time of 261.202 ms. This represents a 66% reduction in boot latency during critical ROM loading phase compared to unoptimized baseline.
Keywords ACAP Versal, AI Engine, Optimize Boot, SoC Heterogeneous, FIR Filter, VCK1902, Vitis, Vivado
Field Engineering
Published In Volume 8, Issue 3, May-June 2026
Published On 2026-06-02
DOI https://doi.org/10.36948/ijfmr.2026.v08i03.80167
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