Emerging Trends in Low Power Vlsiarchitecture for Wsn Application- an Overview

Author(s)	Prof. Seema B S, Dr. Narendra C P
Country	India
Abstract	Wireless sensor network (WSN) is an emerging field which demands an energy efficient ultra-low power VLSI architecture which delivers high performance with less power consumption as most of the sensor nodes are battery operated. An innovative architecture need to be designed which demonstrates circuit level leakage reduction technique with power optimization and complete ASIC implementation for WSN application. There are various techniques such as transistor stacking, MTCMOS, power gating, clock gating, DVFS which are individually used for power optimization. The main aim of this paper is perform a comprehensive study on the works that are been carried out reduce overall power consumption and integrating it with a complete ASIC flow for PPA optimization.
Keywords	Low Power VLSI(Very Large Scale Integration) Design, Wireless Sensor Network , ASIC (Application Specific Integrated Circuits) Implementation, PPA (Power Performance Area) Optimization.
Field	Engineering
Published In	Volume 8, Issue 4, July-August 2026
Published On	2026-07-21
DOI	https://doi.org/10.36948/ijfmr.2026.v08i04.84149

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